Re: Ich empfinde Access incl. MS SQLServer gegenüber Oracle als Spielzeug. - Sicherheitsleck im Application Server vo…

>
> > Hallo,
> > > Der Impuls war der, dass M$ so stur ist und nichts anderes als
> > > Intel kennt…
> > du hattest wohl noch nie die CD von NT 4.0 in Händen und Dir mal
> > die Verzeichnisse neben i386 angesehen.
> Hast du die Ports mal live gesehen? Alpha ging ja noch einigermaßen
> (auch wenn nicht so recht schlüssig war, was ein
> 32Bit-Betriebssystem
> auf einer 64Bit-Architektur soll), die anderen Ports (insbesonere
> PowerPC) waren einfach nur lächerlich. Und ja, ich habe NT auf ‘ner
> RS/6000 gesehen
>
> über den Satz bzgl. der Ahnungslosogkeit sage ich jetzt mal nix
//——————- HankPym
Port auf RS/6000 ???
Alpha ging wegen des Endian-Formats schneller.
Ahnungslos ???
Ja, sicher. Null Plan.
HankPym. *kopfschüttel* über Eure Ahnungslosigkeit.
Es folgt alphaops.h nur die ersten Zeilen. Visual C 4 prof.
mit Lizenz für MS C seit MS C 5.1 .
—————
/*
Copyright (c) 1992-1995 Digital Equipment Corporation
Module Name:
alphaops.h
Abstract:
Alpha AXP instruction and floating constant definitions.
Author:
Revision History:
–*/
#ifndef _ALPHAOPS_
#define _ALPHAOPS_
//
// Instruction types.
// The Alpha architecture does not number the instruction types,
// this numbering is for software decoding only.
//
#define ALPHA_UNKNOWN 0 // Reserved or illegal
#define ALPHA_MEMORY 1 // Memory (load/store)
#define ALPHA_FP_MEMORY 2 // Floating point Memory
#define ALPHA_MEMSPC 3 // Memory special
#define ALPHA_JUMP 4 // Jump (memory formation)
#define ALPHA_BRANCH 5 // Branch
#define ALPHA_FP_BRANCH 6 // Floating Point Branch
#define ALPHA_OPERATE 7 // Register-register operate
#define ALPHA_LITERAL 8 // Literal-register operate
#define ALPHA_FP_OPERATE 9 // Floating point operate
#define ALPHA_FP_CONVERT 10 // Floating point convert
#define ALPHA_CALLPAL 11 // Call to PAL
#define ALPHA_EV4_PR 12 // EV4 MTPR/MFPR PAL mode instructions
#define ALPHA_EV4_MEM 13 // EV4 special memory PAL mode access
#define ALPHA_EV4_REI 14 // EV4 PAL mode switch
//
// Instruction Opcodes.
//
#define CALLPAL_OP 0×00 // ALPHA_CALLPAL
#define _01_OP 0×01 // - reserved opcode
#define _02_OP 0×02 // - reserved opcode
#define _03_OP 0×03 // - reserved opcode
#define _04_OP 0×04 // - reserved opcode
#define _05_OP 0×05 // - reserved opcode
#define _06_OP 0×06 // - reserved opcode
#define _07_OP 0×07 // - reserved opcode
#define LDA_OP 0×08 // ALPHA_MEMORY
#define LDAH_OP 0×09 // ALPHA_MEMORY
#define _0A_OP 0×0A // - reserved opcode
#define LDQ_U_OP 0×0B // ALPHA_MEMORY
#define _0C_OP 0×0C // - reserved opcode
#define _0D_OP 0×0D // - reserved opcode
#define _0E_OP 0×0E // - reserved opcode
#define STQ_U_OP 0×0F // ALPHA_MEMORY
#define ARITH_OP 0×10 // ALPHA_OPERATE or ALPHA_LITERAL
#define BIT_OP 0×11 // ALPHA_OPERATE or ALPHA_LITERAL
#define BYTE_OP 0×12 // ALPHA_OPERATE or ALPHA_LITERAL
#define MUL_OP 0×13 // ALPHA_OPERATE or ALPHA_LITERAL
#define _14_OP 0×14 // - reserved opcode
#define VAXFP_OP 0×15 // ALPHA_FP_OPERATE
#define IEEEFP_OP 0×16 // ALPHA_FP_OPERATE
#define FPOP_OP 0×17 // ALPHA_FP_OPERATE
#define MEMSPC_OP 0×18 // ALPHA_MEMORY
#define PAL19_OP 0×19 // - reserved for PAL mode
//#define MFPR_OP 0×19 // ALPHA_MFPR
#define JMP_OP 0×1A // ALPHA_JUMP
#define PAL1B_OP 0×1B // - reserved for PAL mode
#define _1C_OP 0×1C // - reserved opcode
#define PAL1D_OP 0×1D // - reserved for PAL mode
//#define MTPR_OP 0×1D // ALPHA_MTPR
#define PAL1E_OP 0×1E // - reserved for PAL mode
#define PAL1F_OP 0×1F // - reserved for PAL mode
#define LDF_OP 0×20 // ALPHA_MEMORY
#define LDG_OP 0×21 // ALPHA_MEMORY
#define LDS_OP 0×22 // ALPHA_MEMORY
#define LDT_OP 0×23 // ALPHA_MEMORY
#define STF_OP 0×24 // ALPHA_MEMORY
#define STG_OP 0×25 // ALPHA_MEMORY
#define STS_OP 0×26 // ALPHA_MEMORY
#define STT_OP 0×27 // ALPHA_MEMORY
#define LDL_OP 0×28 // ALPHA_MEMORY
#define LDQ_OP 0×29 // ALPHA_MEMORY
#define LDL_L_OP 0×2A // ALPHA_MEMORY
#define LDQ_L_OP 0×2B // ALPHA_MEMORY
#define STL_OP 0×2C // ALPHA_MEMORY
#define STQ_OP 0×2D // ALPHA_MEMORY
#define STL_C_OP 0×2E // ALPHA_MEMORY
#define STQ_C_OP 0×2F // ALPHA_MEMORY
#define BR_OP 0×30 // ALPHA_BRANCH
#define FBEQ_OP 0×31 // ALPHA_BRANCH
#define FBLT_OP 0×32 // ALPHA_BRANCH
#define FBLE_OP 0×33 // ALPHA_BRANCH
#define BSR_OP 0×34 // ALPHA_BRANCH
#define FBNE_OP 0×35 // ALPHA_BRANCH
#define FBGE_OP 0×36 // ALPHA_BRANCH
#define FBGT_OP 0×37 // ALPHA_BRANCH
#define BLBC_OP 0×38 // ALPHA_BRANCH
#define BEQ_OP 0×39 // ALPHA_BRANCH
#define BLT_OP 0×3A // ALPHA_BRANCH
#define BLE_OP 0×3B // ALPHA_BRANCH
#define BLBS_OP 0×3C // ALPHA_BRANCH
#define BNE_OP 0×3D // ALPHA_BRANCH
#define BGE_OP 0×3E // ALPHA_BRANCH
#define BGT_OP 0×3F // ALPHA_BRANCH
#define LDA_OP_STR “lda”
#define LDAH_OP_STR “ldah”
#define LDQ_U_OP_STR “ldq_u”
#define STQ_U_OP_STR “stq_u”
#define LDF_OP_STR “ldf”
#define LDG_OP_STR “ldg”
#define LDS_OP_STR “lds”
#define LDT_OP_STR “ldt”
#define STF_OP_STR “stf”
#define STG_OP_STR “stg”
#define STS_OP_STR “sts”
#define STT_OP_STR “stt”
#define LDL_OP_STR “ldl”
#define LDQ_OP_STR “ldq”
#define LDL_L_OP_STR “ldl_l”
#define LDQ_L_OP_STR “ldq_l”
#define STL_OP_STR “stl”
#define STQ_OP_STR “stq”
#define STL_C_OP_STR “stl_c”
#define STQ_C_OP_STR “stq_c”
#define BR_OP_STR “br”
#define FBEQ_OP_STR “fbeq”
#define FBLT_OP_STR “fblt”
#define FBLE_OP_STR “fble”
#define BSR_OP_STR “bsr”
#define FBNE_OP_STR “fbne”
#define FBGE_OP_STR “fbge”
#define FBGT_OP_STR “fbgt”
#define BLBC_OP_STR “blbc”
#define BEQ_OP_STR “beq”
#define BLT_OP_STR “blt”
#define BLE_OP_STR “ble”
#define BLBS_OP_STR “blbs”
#define BNE_OP_STR “bne”
#define BGE_OP_STR “bge”
#define BGT_OP_STR “bgt”
//
// Type (1) Memory Instruction Format.
// Type (2) Memory Special Instruction Format.
//
// 3 2 2 2 2 1 1
// 1 6 5 1 0 6 5 0
// ———– ——— ——— ——————————-
// | opcode | Ra | Rb | Memory_disp |
// ———– ——— ——— ——————————-
//
// LDAx Ra.wq,disp.ab(Rb.ab) x = (,H)
// LDx Ra.wq,disp.ab(Rb.ab) x = (L,Q,F,G,S,T)
// LDQ_U Ra.wq,disp.ab(Rb.ab)
// LDx_L Ra.wq,disp.ab(Rb.ab) x = (L,Q)
// STx_C Ra.mq,disp.ab(Rb.ab) x = (L,Q)
// STx Ra.rq,disp.ab(Rb.ab) x = (L,Q,F,G,S,T)
// STQ_U Ra.rq,disp.ab(Rb.ab)
//
typedef struct _Alpha_Memory_Format {
LONG MemDisp : 16;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_Memory_Format;
//
// Special Memory instruction function codes (in Memdisp).
//
#define TRAPB_FUNC 0×0000
#define EXCB_FUNC 0×0400
#define MB_FUNC 0×4000
#define WMB_FUNC 0×4400
#define MB2_FUNC 0×4800
#define MB3_FUNC 0×4C00
#define FETCH_FUNC 0×8000
#define FETCH_M_FUNC 0xA000
#define RPCC_FUNC 0xC000
#define RC_FUNC 0xE000
#define RS_FUNC 0xF000
#define TRAPB_FUNC_STR “trapb”
#define EXCB_FUNC_STR “excb”
#define MB_FUNC_STR “mb”
#define MB1_FUNC_STR “wmb”
#define MB2_FUNC_STR “mb2″
#define MB3_FUNC_STR “mb3″
#define FETCH_FUNC_STR “fetch”
#define FETCH_M_FUNC_STR “fetch_m”
#define RPCC_FUNC_STR “rpcc”
#define RC_FUNC_STR “rc”
#define RS_FUNC_STR “rs”
//
// Type (3) Memory Format Jump Instructions.
//
// 3 2 2 2 2 1 1 1 1
// 1 6 5 1 0 6 5 4 3 0
// ———– ——— ——— — —————————
// | opcode | Ra | Rb |Fnc| Hint |
// ———– ——— ——— — —————————
//
// xxx Ra.wq,(Rb.ab),hint xxx = (JMP, JSR, RET, JSR_COROUTINE)
//
typedef struct _Alpha_Jump_Format {
LONG Hint : 14;
ULONG Function : 2;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_Jump_Format;